The present application relates to semiconductor technology and more particularly to a semiconductor structure containing a high mobility semiconductor channel material, i.e., a III-V semiconductor material, and asymmetrical source/drain regions and a method of forming the same.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continue scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that MOSFETs are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) or semiconductor nanowire or nanowire stack transistors, is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Such non-planar semiconductor devices can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.
In such non-planar semiconductor devices further device improvements can be achieved by utilizing a semiconductor channel material that provides high electron mobility. For example, III-V semiconductor materials are one promising candidate for providing high electron mobility devices. Methods are needed that enable one to form non-planar semiconductor devices that contain such high mobility channel materials without requiring the use of any thick buffer layer that is typically needed for forming such high mobility semiconductor channel materials.